Morphological operations form the basic operations for image processing. For this reason, they are much used in image processing. With the development of multimedia technologies, in particular the enhancement of the image resolutions associated with the miniaturization of electronic circuits, there is now a growing need for optimization of these morphological operations. Today, application specific integrated circuits, or “ASICs”, allow morphological operations to be accelerated. However, an ASIC circuit, on its own, only allows one particular morphological operation to be accelerated. In other words, no ASIC module exists that is actually capable of accelerating several morphological operations. Furthermore, as far as the erosion and expansion operations are concerned, a particular ASIC circuit is only able to perform these operations for a structural element of predefined dimensions, or, at the very least, for structural elements with dimensions smaller than the predefined dimensions. In other words, an ASIC circuit performing an erosion or expansion operation for a structural element of dimensions 3×3 cannot carry out this erosion or expansion operation for a structural element of dimensions 5×5. One solution to these two limitations thus consists in using a programmable processing structure such as a personal computer. However, such a structure exhibits a performance that is greatly inferior to that of ASIC circuits. By way of example, at least three cycles per pixel are required in order to obtain a result with a programmable structure, whereas a result can be obtained for several pixels in a single cycle with certain ASIC circuits.